Layer assembly

ABSTRACT

A device including a locally modified buried first layer. A second layer is arranged on top of the first layer. The first layer includes at least one modified section and at least one unmodified section. The modified material of the locally modified buried first layer changes or induces mechanical strain in a portion of the second layer which is arranged above the at least one modified section. At least one nanostructure is placed on top of the second layer in an area, which is located above the at least one unmodified section of the first layer or adjacent thereto, said at least one nanostructure being formed by a strain-sensitive third material deposited on the locally strained second layer.

The invention relates to layer assemblies and methods for fabricatinglayer assemblies with a deterministic local arrangement on a surface.More specifically, the invention relates to layer assemblies with atleast one locally arranged nanostructure. Hereinafter, the term“nanostructure” refers to structures having a size (diameter) of lessthan 1 μm.

BACKGROUND OF THE INVENTION

Atkinson et al. (Applied Physics Letters, 93, 101908 (2008)) describesthe growth of nanostructures on a pre-structured surface. A localarrangement of single and pairs of InAs quantum dots at ex situ definednanometer sized holes during growth is demonstrated using a GaAs(001)substrate surface which is patterned by electron-beam photolithographyand dry etching.

So far, the step of pre-patterning the surface to obtain localarrangement of nanostructures is done using complex patterningtechniques like electron beam lithography, focussed ion beam etching,ion implantation and the like. The direct surface patterning may causecrystal damages and defects that may have negative impacts on thequality and performance of nanostructures made thereon. Long-rangeimpact of the patterning along the surface normal of a substrate isuseful as it enables the separation of the nanostructures frompatterning-induced defects.

OBJECTIVE OF THE PRESENT INVENTION

An objective of the present invention is to provide a method forfabricating nanostructures with a deterministic local arrangement on asurface and having an improved performance.

A further objective of the present invention is to provide a devicehaving at least one nanostructure with increased performance compared toprior art devices.

BRIEF SUMMARY OF THE INVENTION

An embodiment of the present invention relates to a method offabricating a layer assembly comprising the steps of:

-   -   arranging a first layer on top of a carrier;    -   arranging a second layer on top of the first layer;    -   locally modifying the material of the buried first layer and        providing at least one modified section in the first layer,        wherein the modified material changes or induces mechanical        strain in a portion of the second layer which is arranged above        the at least one modified section;    -   after locally modifying the material of the buried first layer,        depositing a third material on top of the second layer, at least        one characteristic of the third material being sensitive to the        local mechanical strain in the second layer.

An advantage of this embodiment of the invention is that the secondlayer, even if unstructured, exhibits a locally modified characteristicdue to strain caused by the buried first layer. As such, the thirdmaterial, which is deposited thereon, may for instance create one ormore nanostructures even on an unstructured surface. The localisation ofthe nanostructures may simply be caused by the local strain in thesecond layer.

The strain-sensitive characteristic of the third material preferablyrelates to at least one of the following: thickness, composition, shape,electronic band structure, crystal growth.

According to a preferred embodiment, a portion of the second layer isremoved to expose a portion of the buried first layer. For instance, anedge face or side facet of the buried first layer may be exposed.

After partly exposing the buried first layer, the exposed portion (e.g.edge face or side facet) may be chemically modified by applying at leastone chemical, prior to depositing the strainsensitive third material.

The carrier and all layers are preferably crystalline prior to the localmodification of the buried first layer.

At least one nanostructure is preferably formed on top of the secondlayer in an area, which is located above an unmodified section of thefirst layer or adjacent thereto, by depositing the strain-sensitivethird material on the locally strained second layer.

The deposition of the strain-sensitive material may form at least onesemiconductor nanostructure with quantized energy levels. For instance,the nanostructures may be quantum wells, quantum wires, or quantum dots.

Preferably, the layer assembly includes at least one nanostructure thatforms at least one photon emitter. The photon emitter may be a singlephoton emitter.

By removing portions of the first and second layers, a mesa structuremay be provided that includes the buried first layer and the secondlayer.

One or more chemicals are preferably applied to the edge face or sidefacet of the mesa structure, prior to depositing the third material.

The chemicals preferably modify the material of the buried first layerin an outer section adjacent to the outer surface of the mesa structure,said outer section embracing an inner section of the mesa structure. Thematerial of the buried first layer in the inner section of the mesastructure, however, remains unchanged.

The inner contour of the outer section preferably exhibits at least onecorner. A corner in the contour marks a point of very high strain in thesecond layer, and thus supports the local arrangement of nanostructuresduring deposition. The inner contour may exhibit a square, a triangle, arectangle or any other cornered shape.

The material of the buried first layer in the outer section ispreferably oxidized, nitridated, or carbonized.

The modification of the buried first layer in the outer sectionpreferably increases or decreases the volume of the material in theouter section and thereby locally induces mechanical strain inside thesecond layer.

At least one nanostructure may be formed on top of the second layer inan area, which is located above the inner unmodified section of thefirst layer or adjacent thereto, by depositing the third material on thelocally strained second layer.

Furthermore, electrical contacts are preferably added which allowapplying an electrical voltage to the resulting layer assembly.

According to a further preferred embodiment, the modification of thematerial of the buried first layer in the outer section decreases theelectrical conductivity in the outer section such that the inner sectionof the buried first layer forms a current guiding aperture that ispositioned below the at least one nanostructure.

The buried first layer may be an Al(Ga)As-layer. After locally modifyingthe Al(Ga)As-layer, III/V compound materials may be deposited as thirdmaterial.

Alternatively, the buried first layer may be an AlInN-layer. Afterlocally modifying the AlInN-layer, III/V compound materials may bedeposited as third material.

The carrier is preferably a crystalline silicon substrate or any othersubstrate which allows epitaxial growth of semiconductors such assapphire, silicon carbide, zinc oxide, spinel, gallium phosphide,gallium arsenide, or indium phosphide.

Furthermore, one or more intermediate layers may be arranged between thecarrier and the first layer, between the second layer and the firstlayer and/or between the third material and the second layer.

Each of the first and second layers may consist of one or moresublayers.

A further embodiment of the invention relates to a device comprising: alocally modified buried first layer, said first layer comprising atleast one modified section and at least one unmodified section; a secondlayer which is arranged on top of the first layer; wherein the modifiedmaterial of the locally modified buried first layer changes or inducesmechanical strain in a portion of the second layer which is arrangedabove the at least one modified section; and wherein at least onenanostructure is placed on top of the second layer in an area, which islocated above the at least one unmodified section of the first layer oradjacent thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the manner in which the above-recited and other advantagesof the invention are obtained will be readily understood, a moreparticular description of the invention briefly described above will berendered by reference to specific embodiments thereof which areillustrated in the appended figures. Understanding that these figuresdepict only typical embodiments of the invention and are therefore notto be considered to be limiting of its scope, the invention will bedescribed and explained with additional specificity and detail by theuse of the accompanying drawings in which

FIG. 1 shows in an exemplary fashion a layer stack for fabricating asingle photon emitter,

FIG. 2 shows the layer stack of FIG. 1 after etching a mesa structure,

FIG. 3 shows the mesa structure of FIG. 2 after oxidizing an outersection thereof,

FIG. 4 shows the curved surface of the mesa structure of FIG. 3 afterthe oxidation in a schematic fashion,

FIG. 5 shows the mesa structure of FIG. 4 after depositingnanostructures,

FIG. 6 shows the mesa structure of FIG. 4 including the nanostructuresin a top view,

FIG. 7 shows the mesa structure including the nanostructures of FIG. 5after depositing a cap layer, and

FIG. 8 shows the calculated strain distribution in the mesa structure ofFIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will be bestunderstood by reference to the drawings, wherein identical or comparableparts are designated by the same reference signs throughout. It will bereadily understood that the present invention, as generally describedherein, could vary in a wide range. Thus, the following more detaileddescription of the exemplary embodiments of the present invention, isnot intended to limit the scope of the invention, as claimed, but ismerely representative of presently preferred embodiments of theinvention.

An exemplary embodiment of a method for fabricating at least one photonemitter will be explained hereinafter referring to FIGS. 1-8.

As shown in FIG. 1, a GaAs intermediate buffer layer 10 is grown bymetalorganic vapor phase epitaxy (MOVPE) on a carrier 20. The carrier 20may consist of or comprise a vicinal GaAs(b 001) substrate 20. The MOVPEstep may be carried out in a commercial Aixtron AIX200/4 reactor. Thegrowth conditions may be chosen similar to standard growth conditionsfor MOVPE growth of AlAs/GaAs as known in the art. Other epitaxialgrowth techniques and their respective growth conditions arecontemplated as well.

Then, a first layer 30 is deposited on the intermediate buffer layer 10.The first layer 30 may consist of a plurality of AlGaAs-sublayers. Forinstance, the first layer 30 may comprise a gradedAl_(0-0.9)Ga_(1-0.1)As sublayer 31 (preferred thickness between 1 nm and100 nm, e.g. 30 nm), an Al_(0.9)Ga_(0.1)As sublayer 32 (preferredthickness between 10 nm and 100 nm, e.g. 40 nm), an AlAs sublayer33(preferred thickness between 1 nm and 100 nm, e.g. 30 nm), anAl_(0.9)Ga_(0.1)As sublayer 34 (preferred thickness between 10 nm and100 nm, e.g. 40 nm), and an oppositely graded Al_(0.9-0)Ga_(0.1-1) Assublayer 35 (preferred thickness between 1 nm and 100 nm, e.g. 30 nm).

The growth is concluded by depositing a second layer 40 which mayconsist of a GaAs material (preferred thickness between 5 nm and 200 nm,e.g. 100 nm). The resulting layer structure is shown in FIG. 1.

Referring to FIG. 2, after the epitaxy, a circular mesa structure 50 of15-25 μm diameter is defined by conventional photolithography andreactive ion etching, for example. The mesa height is preferably chosensuch that the side facets 30 a of the first layer 30 are completely orat least partly exposed.

Afterwards, the material of the exposed side facets 30 a of the firstlayer 30 is oxidized into AlO_(x) as shown in FIG. 3. The oxidation maybe carried out using nitrogen as carrier gas and water vapor asoxidizing agent. During oxidation, the reactor may be held at 50 mbartotal pressure while the mesa structure 50 is heated to 450° C. Amixture of 3 slpm nitrogen and 50 sccm water vapor is then supplied tothe mesa structure 50. These conditions lead to a reaction-ratecontrolled anisotropic oxidation of the first layer 30. The oxidation ispreferably stopped at an oxidation depth of 7-8 μm. The resulting innercontour of the oxidized layer is square-like due to the anisotropiccharacter of the oxidation. Other inner contours of the oxidized layermay be obtained using other mesa shapes and/or other oxidationconditions.

In case of an isotropic oxidation, the outer contour of the mesastructure 50 that is defined by photolithography and etching, decidesabout the inner contour of the oxidized layer. As such, in case ofisotropic oxidation, the outer contour of the mesa structure preferablycomprises at least one corner in order to obtain an inner contour withat least one corner. For instance, if one likes to achieve a square-likeinner contour a square-like outer contour needs to be chosen for themesa structure 50.

The oxidation of the buried first layer 30 forms an outer section 51adjacent to the outer surface of the mesa structure 50. The outersection 51 provides a high electrical resistance due to the oxidation,and embraces an inner section 52 of the mesa structure 50. The innersection 52 remains unchanged (not-oxidized) and preferably exhibits alow electrical resistance due to sufficient doping. As such, the innersection 52 forms a current aperture 60 having a cornered (e.g.square-like) shape.

As shown in a schematic fashion in FIG. 4, the oxidation leads to asurface height modulation of the second layer 40 over the aperture 60.The surface height modulation results from the fact that the oxidationof the buried first layer 30 decreases the volume of the material in theouter section 51 and thereby locally induces mechanical strain insidethe second layer 40.

The distribution of the mechanical strain ε_(xx) and ε_(yy) at thesurface of the second layer 40 is shown in FIG. 8 for differentdiameters of the current aperture 60. It can be seen that the strain andthe strain distribution can be adjusted by choosing appropriatediameters. A long-range impact of the order of 50-300 nm of the strainalong the surface normal is also observed.

The oxidized mesa structure 50 is then loaded back into a MOVPE reactorfor subsequent overgrowth with at least one semiconductor nanostructurewith quantized energy levels.

The semiconductor nanostructure growth sequence may start with a bakeout at a temperature between 700° C. and 800° C. (preferably 715° C.)for 5 minutes under arsenic atmosphere followed by growth of a GaAsbuffer layer (preferred thickness between 10 nm and 100 nm, e.g. 50 nm;preferred growth temperature between 600° C. and 700° C., e.g. 685° C.).The mentioned GaAs-buffer layer is preferred but not mandatory, and istherefore not shown in the Figures.

The temperature is subsequently lowered to approximately 500° C. (e.g.515° C.) for nanostructure growth. The nanostructures are obtained afterinitial deposition of a 2 monolayer thick In_(0.75)Ga_(0.25)As layerwhich is about the critical thickness for a 2D/3D transition (see FIG.5). The transition from a two-dimensional layer to a three-dimensionalnanostructure is governed by the Stranski-Krastanov growth. Under theconditions described above the nanostructure densities is typically inthe range between 10⁸ cm⁻² and 10⁷ cm⁻². The resulting nanostructuresare marked with reference numeral 70 in FIG. 5.

FIG. 6 shows a top view of the oxidized mesa structure 50, the buriedsquare-like current aperture 60, and the nanostructures 70 on top of thesecond layer 40. The nanostructures 70 are primarily formed above thecorners 61 of the square-like current aperture 60 due to the mechanicalstrain enhancement which is localized in the corners 61.

Preferably, a growth interruption without arsenic stabilization may beapplied afterwards before finally growing a GaAs cap layer 80 (preferredthickness between 1 nm and 100 nm, e.g. 40 nm). The resulting photonemitter device 100 is shown in FIG. 7 before adding electrical contacts.

The method as described above yields a plurality of advantages comparedto prior art methods:

-   1. The nanostructures 70 may be deposited on an unstructured surface    of the second layer 40. The local arrangement of the nanostructures    70 is defined by mechanical strain caused by the buried first layer    30 which is located below the second layer 40. As such, the    nanostructures 70 may grow on a surface which is defect-free or at    least may be almost defect-free.-   2. The inner section 52 of the mesa structure 50 provides    self-alignment of the current aperture 60 with respect to the    nanostructures 70. Therefore, the nanostructures 70 are    automatically positioned above the current aperture 60 and subject    to focused current injection. The efficiency of the current    injection is thus optimized.-   3. The local arrangement of the nanostructures on a nanometer scale    is obtained without using complex lithographic and etching    procedures to prepare nanometer-sized surface areas.    Reference Signs-   10 buffer layer-   20 carrier-   30 first layer-   30 a side facet-   31-35 sublayers of the first layer-   40 second layer-   50 mesa structure-   51 outer section-   52 inner section-   60 current aperture-   61 corner-   ε_(xx), ε_(yy) mechanical strain-   70 nanostructure-   80 cap layer-   100 photon emitter device

The invention claimed is:
 1. A device comprising: a locally modifiedburied first layer, said first layer comprising at least one modifiedsection and at least one unmodified section; a second layer which isarranged on top of the first layer; wherein the modified material of thelocally modified buried first layer changes or induces mechanical strainin a portion of the second layer which is arranged above the at leastone modified section; and wherein at least one nanostructure is placedon top of the second layer in an area, which is located above the atleast one unmodified section of the first layer or adjacent thereto,said at least one nanostructure being formed by a strain-sensitive thirdmaterial deposited on the locally strained second layer.
 2. The deviceof claim 1 wherein the nanostructure is self-aligned above theunmodified section of the first layer.
 3. The device of claim 1 whereinthe device forms a single photon emitter or an entangled photon pairemitter.
 4. The device of claim 1 wherein said at least onenanostructure forms a single photon emitter.
 5. The device of claim 1wherein said at least one nanostructure comprises a quantum well,quantum wire, or quantum dot.
 6. The device of claim 1 wherein thethickness of the first layer in the modified section differs from thethickness of the first layer in the unmodified section.
 7. The device ofclaim 1 further comprising a mesa structure that includes the buriedfirst layer and the second layer.
 8. The device of claim 7 wherein saidmodified section of the buried first layer forms an outer sectionadjacent to the outer surface of the mesa structure, and said unmodifiedsection of the buried first layer forms an inner section of the mesastructure.
 9. The device of claim 8 wherein the thickness of the buriedfirst layer in the outer section of the mesa structure differs from thethickness of the buried first layer in the inner section of the mesastructure and thereby locally induces mechanical strain inside thesecond layer.
 10. The device of claim 9 wherein the inner contour of theouter section comprises at least one corner.
 11. The device of claim 10wherein the inner contour exhibits a square, a triangle or a rectangleshape.
 12. The device of claim 8 wherein the material of the buriedfirst layer in the outer section has a smaller electrical conductivitythan the material of the inner section of the buried first layer, bothsections forming a current guiding aperture that is positioned below theat least one nanostructure.
 13. The device of claim 1 wherein the devicecomprises a cap layer on top of said at least one nanostructure.
 14. Thedevice of claim 1 wherein the material of the buried first layer in themodified section is an oxidized, a nitridated, or a carbonized material.15. The device of claim 1 wherein the at least one semiconductornanostructure has quantized energy levels.
 16. The device of claim 1further comprising electrical contacts which allow applying anelectrical voltage.
 17. The device of claim 1 further comprising acurrent guiding aperture that is positioned below the at least onenanostructure.
 18. The device of claim 1 wherein the material of theburied first layer is Al(Ga)As-material or AlInN-material.
 19. Thedevice of claim 1 wherein at least one intermediate layer is arrangedbetween the carrier and the first layer, between the second layer andthe first layer and/or between the third material and the second layer.20. The device of claim 1 wherein said modified section of the buriedfirst layer is a chemically modified section.